[Beignet] [PATCH 5/5] GBE: we no longer need to allocate register from two directions.

[Zhigang Gong]

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/backend/context.hpp            | 2 +-
 backend/src/backend/gen_reg_allocation.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/backend/src/backend/context.hpp b/backend/src/backend/context.hpp
index e1f5a71..04bcf43 100644
--- a/backend/src/backend/context.hpp
+++ b/backend/src/backend/context.hpp
@@ -85,7 +85,7 @@ namespace gbe
       return JIPs.find(insn) != JIPs.end();
     }
     /*! Allocate some memory in the register file */
-    int16_t allocate(int16_t size, int16_t alignment, bool bFwd=0);
+    int16_t allocate(int16_t size, int16_t alignment, bool bFwd = true);
     /*! Deallocate previously allocated memory */
     void deallocate(int16_t offset);
     /*! Spilt a block into 2 blocks, for some registers allocate together but  deallocate seperate */
diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index 06f6cc7..bf2ac2b 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -1020,7 +1020,7 @@ namespace gbe
     using namespace ir;
 
     if (ctx.reservedSpillRegs != 0) {
-      reservedReg = ctx.allocate(ctx.reservedSpillRegs * GEN_REG_SIZE, GEN_REG_SIZE);
+      reservedReg = ctx.allocate(ctx.reservedSpillRegs * GEN_REG_SIZE, GEN_REG_SIZE, false);
       reservedReg /= GEN_REG_SIZE;
     } else {
       reservedReg = 0;
-- 
1.9.1