[Beignet] [PATCH 1/8] [OCL20] support generic atomic.

[xionghu.luo at intel.com]

From: Luo Xionghu <xionghu.luo at intel.com>

Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index cc0ace0..14a1930 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -5654,8 +5654,19 @@ namespace gbe
         if (addrBytes == 8)
           addrDW = convertU64ToU32(sel, address);
         sel.ATOMIC(dst, genAtomicOp, msgPayload, addrDW, src1, src2, GenRegister::immud(0xfe), sel.getBTITemps(AM));
-      }
-      else
+      } else if (addrSpace == ir::MEM_GENERIC) {
+          Register localMask = generateLocalMask(sel, address);
+          sel.push();
+            sel.curr.useVirtualFlag(localMask, GEN_PREDICATE_NORMAL);
+            GenRegister addrDW = address;
+            if (addrBytes == 8)
+              addrDW = convertU64ToU32(sel, address);
+            sel.ATOMIC(dst, genAtomicOp, msgPayload, addrDW, src1, src2, GenRegister::immud(0xfe), sel.getBTITemps(AM));
+
+            sel.curr.inversePredicate = 1;
+            untypedAtomicA64Stateless(sel, insn, msgPayload, dst, address, src1, src2, GenRegister::immud(0xff));
+          sel.pop();
+      } else
         untypedAtomicA64Stateless(sel, insn, msgPayload, dst, address, src1, src2, GenRegister::immud(0xff));
 
       markAllChildren(dag);
-- 
2.1.4