[Beignet] [PATCH 4/4] Backend: Code clean related to workgroup reduce

[grigore.lupescu at intel.com]

From: Grigore Lupescu <grigore.lupescu at intel.com>

---
 backend/src/backend/gen_context.cpp        |  27 --------
 backend/src/backend/gen_insn_selection.cpp | 100 -----------------------------
 2 files changed, 127 deletions(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 6ad5977..13fcce7 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -2967,33 +2967,6 @@ namespace gbe
     p->pop();
 }
 
-#define SEND_RESULT_MSG() \
-do { \
-  p->push(); { /* then send msg. */ \
-    p->curr.noMask = 1; \
-    p->curr.predicate = GEN_PREDICATE_NONE; \
-    p->curr.execWidth = 1; \
-    GenRegister offLen = GenRegister::retype(GenRegister::offset(nextThreadID, 0, 20), GEN_TYPE_UD); \
-    offLen.vstride = GEN_VERTICAL_STRIDE_0; \
-    offLen.width = GEN_WIDTH_1; \
-    offLen.hstride = GEN_HORIZONTAL_STRIDE_0; \
-    uint32_t szEnc = typeSize(theVal.type) >> 1; \
-    if (szEnc == 4) { \
-      szEnc = 3; \
-    } \
-    p->MOV(offLen, GenRegister::immud((szEnc << 8) | (nextThreadID.nr << 21))); \
-    \
-    GenRegister tidEuid = GenRegister::retype(GenRegister::offset(nextThreadID, 0, 16), GEN_TYPE_UD); \
-    tidEuid.vstride = GEN_VERTICAL_STRIDE_0; \
-    tidEuid.width = GEN_WIDTH_1; \
-    tidEuid.hstride = GEN_HORIZONTAL_STRIDE_0; \
-    p->SHL(tidEuid, tidEuid, GenRegister::immud(16)); \
-    \
-    p->curr.execWidth = 8; \
-    p->FWD_GATEWAY_MSG(nextThreadID, 2); \
-  } p->pop(); \
-} while(0)
-
 /**
  * Basic idea:
  * 1. All the threads firstly calculate the max/min/add value for the
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 6ad4447..743cdfe 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -6073,106 +6073,6 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
   /*! WorkGroup instruction pattern */
   DECL_PATTERN(WorkGroupInstruction)
   {
-    INLINE bool storeThreadID(Selection::Opaque &sel, uint32_t slmAddr) const
-    {
-      using namespace ir;
-      GenRegister sr0_0 = GenRegister::retype(GenRegister::sr(0), GEN_TYPE_UW);
-      const uint32_t simdWidth = sel.ctx.getSimdWidth();
-      GenRegister tmp;
-      GenRegister addr;
-      vector<GenRegister> fakeTemps;
-
-      if (simdWidth == 16) {
-        tmp = GenRegister::retype(sel.selReg(sel.reg(FAMILY_WORD), ir::TYPE_U16), GEN_TYPE_UD);
-        addr = GenRegister::retype(sel.selReg(sel.reg(FAMILY_WORD), ir::TYPE_U16), GEN_TYPE_UD);
-      } else {
-        tmp = GenRegister::retype(sel.selReg(sel.reg(FAMILY_DWORD), ir::TYPE_U32), GEN_TYPE_UD);
-        addr = GenRegister::retype(sel.selReg(sel.reg(FAMILY_DWORD), ir::TYPE_U32), GEN_TYPE_UD);
-      }
-
-      sr0_0 = GenRegister::vec1(sr0_0);
-      sel.push(); {
-        sel.curr.predicate = GEN_PREDICATE_NONE;
-        sel.curr.noMask = 1;
-        sel.curr.execWidth = 8;
-
-        sel.MOV(tmp, sr0_0);
-
-        sel.MUL(addr, sel.selReg(ocl::threadid, ir::TYPE_U32), GenRegister::immud(2));
-        sel.ADD(addr, addr, GenRegister::immud(slmAddr));
-
-        sel.push(); {
-          sel.curr.predicate = GEN_PREDICATE_NONE;
-          sel.curr.noMask = 1;
-          sel.push(); {
-            sel.curr.execWidth = 1;
-            sel.MOV(GenRegister::flag(0, 1), GenRegister::immuw(0x01));
-          } sel.pop();
-          sel.curr.flag = 0;
-          sel.curr.subFlag = 1;
-          sel.curr.predicate = GEN_PREDICATE_NORMAL;
-          sel.BYTE_SCATTER(addr, tmp, 1, GenRegister::immw(0xfe), fakeTemps);
-        } sel.pop();
-      } sel.pop();
-      return true;
-    }
-
-    INLINE GenRegister getNextThreadID(Selection::Opaque &sel, uint32_t slmAddr) const
-    {
-      using namespace ir;
-      const uint32_t simdWidth = sel.ctx.getSimdWidth();
-      GenRegister addr;
-      GenRegister nextThread;
-      GenRegister tid;
-      vector<GenRegister> fakeTemps;
-
-      if (simdWidth == 16) {
-        addr = GenRegister::retype(sel.selReg(sel.reg(FAMILY_WORD), ir::TYPE_U16), GEN_TYPE_UD);
-        nextThread = GenRegister::retype(sel.selReg(sel.reg(FAMILY_WORD), ir::TYPE_U16), GEN_TYPE_UD);
-        tid = GenRegister::retype(sel.selReg(sel.reg(FAMILY_WORD), ir::TYPE_U16), GEN_TYPE_UD);
-      } else {
-        addr = sel.selReg(sel.reg(FAMILY_DWORD), ir::TYPE_U32);
-        nextThread = sel.selReg(sel.reg(FAMILY_DWORD), ir::TYPE_U32);
-        tid = sel.selReg(sel.reg(FAMILY_DWORD), ir::TYPE_U32);
-      }
-
-      sel.push(); {
-        sel.curr.execWidth = 8;
-        sel.curr.predicate = GEN_PREDICATE_NONE;
-        sel.curr.noMask = 1;
-        sel.ADD(nextThread, sel.selReg(ocl::threadid, ir::TYPE_U32), GenRegister::immud(1));
-
-        /* Wrap the next thread id. */
-        sel.push(); {
-          sel.curr.predicate = GEN_PREDICATE_NONE;
-          sel.curr.noMask = 1;
-          sel.curr.flag = 0;
-          sel.curr.subFlag = 1;
-          sel.CMP(GEN_CONDITIONAL_EQ, nextThread, sel.selReg(ocl::threadn, ir::TYPE_U32), GenRegister::null());
-          sel.curr.predicate = GEN_PREDICATE_NORMAL;
-          sel.MOV(nextThread, GenRegister::immud(0));
-        } sel.pop();
-
-        sel.MUL(addr, nextThread, GenRegister::immud(2));
-        sel.ADD(addr, addr, GenRegister::immud(slmAddr));
-
-        sel.push(); {
-          sel.curr.predicate = GEN_PREDICATE_NONE;
-          sel.curr.noMask = 1;
-          sel.push(); {
-            sel.curr.execWidth = 1;
-            sel.MOV(GenRegister::flag(0, 1), GenRegister::immuw(0x010));
-          } sel.pop();
-          sel.curr.flag = 0;
-          sel.curr.subFlag = 1;
-          sel.curr.predicate = GEN_PREDICATE_NORMAL;
-          sel.BYTE_GATHER(tid, addr, 1, GenRegister::immw(0xfe), fakeTemps);
-        } sel.pop();
-
-      } sel.pop();
-      return tid;
-    }
-
     /* SLM bassed communication between threads, most of the logic bellow */
     INLINE bool emitWGReduce(Selection::Opaque &sel, const ir::WorkGroupInstruction &insn) const
     {
-- 
2.5.0