[Beignet] [PATCH] keep GEN IR as SSA style

[Guo, Yejun]

---
 backend/src/llvm/llvm_gen_backend.cpp | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index 831666e..31b8bf2 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -2984,10 +2984,12 @@ namespace gbe
           this->newRegister(const_cast<GlobalVariable*>(&v));
           ir::Register reg = regTranslator.getScalar(const_cast<GlobalVariable*>(&v), 0);
           ir::Constant &con = unit.getConstantSet().getConstant(v.getName());
-          ctx.LOADI(getType(ctx, v.getType()), reg, ctx.newIntegerImmediate(con.getOffset(), getType(ctx, v.getType())));
           if (!legacyMode) {
-            ctx.ADD(getType(ctx, v.getType()), reg, ir::ocl::constant_addrspace, reg);
-          }
+            ir::Register regload = ctx.reg(getFamily(getType(ctx, v.getType())));
+            ctx.LOADI(getType(ctx, v.getType()), regload, ctx.newIntegerImmediate(con.getOffset(), getType(ctx, v.getType())));
+            ctx.ADD(getType(ctx, v.getType()), reg, ir::ocl::constant_addrspace, regload);
+          } else
+            ctx.LOADI(getType(ctx, v.getType()), reg, ctx.newIntegerImmediate(con.getOffset(), getType(ctx, v.getType())));
         }
       } else if(addrSpace == ir::MEM_PRIVATE) {
           this->newRegister(const_cast<GlobalVariable*>(&v));
-- 
2.7.4