[Beignet] [PATCH] keep GEN IR as SSA style

[Yang, Rong R]

LGTM, pushed, thanks.
Please add Signed-off-by message next time.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Guo, Yejun
> Sent: Wednesday, June 7, 2017 15:44
> To: beignet at lists.freedesktop.org
> Cc: Guo, Yejun <yejun.guo at intel.com>
> Subject: [Beignet] [PATCH] keep GEN IR as SSA style
> 
> ---
>  backend/src/llvm/llvm_gen_backend.cpp | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/backend/src/llvm/llvm_gen_backend.cpp
> b/backend/src/llvm/llvm_gen_backend.cpp
> index 831666e..31b8bf2 100644
> --- a/backend/src/llvm/llvm_gen_backend.cpp
> +++ b/backend/src/llvm/llvm_gen_backend.cpp
> @@ -2984,10 +2984,12 @@ namespace gbe
>            this->newRegister(const_cast<GlobalVariable*>(&v));
>            ir::Register reg =
> regTranslator.getScalar(const_cast<GlobalVariable*>(&v), 0);
>            ir::Constant &con = unit.getConstantSet().getConstant(v.getName());
> -          ctx.LOADI(getType(ctx, v.getType()), reg,
> ctx.newIntegerImmediate(con.getOffset(), getType(ctx, v.getType())));
>            if (!legacyMode) {
> -            ctx.ADD(getType(ctx, v.getType()), reg, ir::ocl::constant_addrspace,
> reg);
> -          }
> +            ir::Register regload = ctx.reg(getFamily(getType(ctx, v.getType())));
> +            ctx.LOADI(getType(ctx, v.getType()), regload,
> ctx.newIntegerImmediate(con.getOffset(), getType(ctx, v.getType())));
> +            ctx.ADD(getType(ctx, v.getType()), reg, ir::ocl::constant_addrspace,
> regload);
> +          } else
> +            ctx.LOADI(getType(ctx, v.getType()), reg,
> ctx.newIntegerImmediate(con.getOffset(), getType(ctx, v.getType())));
>          }
>        } else if(addrSpace == ir::MEM_PRIVATE) {
>            this->newRegister(const_cast<GlobalVariable*>(&v));
> --
> 2.7.4
> 
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