Intel DRM driver for SNB

Zhenyu Wang zhenyuw at
Mon Dec 6 22:00:56 PST 2010

On 2010.12.06 15:18:02 -0800, Segovia, Benjamin wrote:
> Hello all,
> is the kernel driver configured to support reads/writes to LLC (last level cache i.e. L3) on SNB?

Now it's under limited use for the buffer that is sure to be cached,
e.g hw status page, etc. code lives in drivers/char/agp/intel-gtt.c.

Open Source Technology Center, Intel ltd.

$gpg --keyserver --recv-keys 4D781827
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