[Bug 32271] DDX opcode is not implemented in radeon shader compiler

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Sat Dec 11 01:59:59 PST 2010


--- Comment #4 from Marek Olšák <maraeo at gmail.com> 2010-12-11 01:59:58 PST ---
(In reply to comment #3)
> (In reply to comment #2)
> > I wonder if lowering DDX/DDY to SFL makes any difference compared to using a
> > shader that outputs (0,0,0,1).
> The lowering pass I was referring to would happen long before the Mesa IR
> level.  At that point there is no SFL instruction.  We'd just replace the
> ir_unop_dFdx and ir_unop_dFdy expressions with constants of 0 in the
> appropriate type.  Backends (e.g., ir_to_mesa) can convert these constants to
> whatever is appropriate.  This way backends for GPUs that can't handle these
> operations will never even see them.  That is, after all, the whole point of
> the various lowering passes in the GLSL compiler. :)

I meant that it's no longer lowering when you replace a function that returns X
with another function that returns 0. It's an incorrect transformation that
changes the code to something completely different. Think of my "lowering to
SFL" as a way to describe what is going on.

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