[Bug 48880] Set mode has different timings than requested on VGA

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Thu Apr 19 08:15:14 PDT 2012


--- Comment #23 from Luc Verhaegen <libv at skynet.be> 2012-04-19 08:15:14 PDT ---
(In reply to comment #21)
> (In reply to comment #20)
> > What about the BIOS bug angle? Because kernel is not setting up the hardware
> > directly, but asking the BIOS to do it, right? Is that out of the question?
> It's not out of the question, but I highly doubt it.  The driver calculates the
> pll dividers and the atom table basically writes them to the pll registers.  If
> there was a bug in the table, I'd expect it to cause problems across the board,
> not just on one mode on one monitor.  We've had lots of these kind of bugs over
> the course of the driver's life.  Some combinations of dividers and monitors
> are just not happy.  The trick is to tweak the algo just enough to fix the
> problematic monitor while not breaking others.  I'll test
> RADEON_PLL_USE_FRAC_FB_DIV on the hw I have here and if all goes well, I'll
> send it to Dave.

The trick is testing a given version of the chip to the death and finding the
frequency limits of the inner loop of the pll. I have always managed to fully
clamp down pll ranges with a halfway decent CRT. It does take time and a
structured approach though.

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