[PATCH] radeon: fix tile_split of 128-bit surface formats with 8x MSAA

[Paul Menzel]

Dear Marek,


Am Dienstag, den 16.10.2012, 02:21 +0200 schrieb Marek Olšák:
> The calculation led to the number 8192, which is too high.

what is the reason it is limited to 4096? Hardware limitation?

What are the ramifications? GPU hangs, rendering errors?

> ---
>  radeon/radeon_surface.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
> index 66c2444..eb587d2 100644
> --- a/radeon/radeon_surface.c
> +++ b/radeon/radeon_surface.c
> @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
>          } else {
>              /* tile split must be >= 256 for colorbuffer surfaces */
>              surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
> +            if (surf->tile_split > 4096)
> +                surf->tile_split = 4096;
>          }
>      } else {
>          /* set tile split to row size */


Thanks,

Paul
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