drm/msm/dsi: hs_zero timing
werner.johansson at gmail.com
Wed Aug 26 18:42:53 PDT 2015
On Aug 26, 2015 11:31 AM, "Rob Clark" <robdclark at gmail.com> wrote:
> I'm not completely sure.. I did observe that we calculated slightly
> different settings w/ the auo novatek panel on z3, compared to what
> downstream had hard-coded in dts (which presumably came from
> magic-spreadsheet), because (I think) of rounding mode->clock to
> integer KHz. Although in the case of the z3 panel, it didn't seem to
> matter. What I am unsure about is whether other panels might be more
> sensitive to different settings.
Yes, the code definitely calculates different timing (as can be seen with
the calculations for this particular Panasonic panel as well). We need more
of the spreadsheet magic in the code it seems. This hs_zero issue seems to
be a bug of sorts inside the MSM SoC itself though, not an issue with the
panel (as exactly the same issue occurred with all three panels I tried.
The "every-eighth value fails" failure mode does not seem to be timing
related as I was able to fuzz the timing way outside of the specified
ranges and still have perfectly good display, as long as I stayed out of
the "every-eighth" value for hs_zero. The panels are typically not crystal
controlled so their frequency tolerances are wide.
The display mode seems a bit over-specified, can we derive clock from
htotal * vtotal * refreshrate instead and get the resolution needed (for
DSI that should always result in the correct clock, right)?
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the dri-devel