[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #32 from Christian König <deathsimple at vodafone.de> ---
(In reply to Chernovsky Oleg from comment #31)
> Tried to launch vdpau-accelerated mpv with fglrx driver and mmiotrace.
> Interesting, the CG_UPLL_FUNC_CNTL always has flags 0x100 | 0x600
> 
> R 4 456.556542 1 0xf0000634 0x707 0x0 0
> W 4 456.556547 1 0xf0000634 0x705 0x0 0
> R 4 456.556553 1 0xf0000634 0x705 0x0 0
> W 4 456.556576 1 0xf0000634 0x705 0x0 0
> R 4 456.556688 1 0xf0000634 0x705 0x0 0
> W 4 456.556693 1 0xf0000634 0x705 0x0 0
> R 4 456.556709 1 0xf0000634 0x705 0x0 0
> R 4 456.556725 1 0xf0000634 0x705 0x0 0
> W 4 456.556730 1 0xf0000634 0x705 0x0 0
> R 4 456.556771 1 0xf0000634 0x705 0x0 0
> W 4 456.556776 1 0xf0000634 0x704 0x0 0
> R 4 456.556837 1 0xf0000634 0x704 0x0 0
> W 4 456.556842 1 0xf0000634 0x700 0x0 0
> W 4 456.556847 1 0xf0000634 0x708 0x0 0
> 
> Any ideas what can 0x100 mask be for?

Strange, the hardware docs say this is for routing the reset signal and
shouldn't be touched by the driver, e.g. it should always be 1.

Is that bit 0 when you use the open source driver?

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