[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #33 from Chernovsky Oleg <adonai at xaker.ru> ---
Yep, I rechecked it and it seems set to 1 always...

Anyway I gathered around 18 Mb of mmiotrace logs to investigate. Now digging
through divider and clock registers.

P.S. I only fear that maybe I launched mmiotrace too late, I did rmmod and then
modprobe fglrx again. Could it setup any registers at the first run? Because at
second it touched UVD only when I launched mpv.

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