[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #16 from Alex Deucher <alexdeucher at gmail.com> ---
(In reply to Christian König from comment #14)
> (In reply to Öyvind Saether from comment #13)
> > on 3.18.1, could this be because the card is factory overclocked?
> 
> Yes, that's possible. If you activate UVD you must downclock the system
> clock for it to work reliable. Not sure if we have implemented that
> correctly for SI.

We already handle it.  SI has UVD power states which also include validated
sclk and mclk levels that are often different than the performance state.  The
driver switches to those states when UVD is used.  At driver load time (when
the ring and IB tests are done), the hw is still in the boot state (which has
really low clocks) anyway.

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