[PATCH v2] drm/fsl-dcu: Fix endian issue when using clk_register_divider

[Meng Yi]

While clk_register_divider will write register as little endian,
Modified the param "shift" from 0 to 24 since DCU is big endian.
Or reg "DCU_DIV_RATIO" will be seted as a incorrect value which
will cause vblank timing issue etc.

Signed-off-by: Meng Yi <meng.yi at nxp.com>
---
Changes in V2:
-check the soc name to decide the "shift" value
 since vf610's divider reg is little endian while
 ls1021a's divider reg is big endian
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..a590ce8 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -386,7 +386,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 	snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
 	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
 			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
-			0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+			!strcmp(fsl_dev->soc->name, "ls1021a")?24:0, 8,
+			CLK_DIVIDER_ROUND_CLOSEST, NULL);
 	if (IS_ERR(fsl_dev->pix_clk)) {
 		dev_err(dev, "failed to register pix clk\n");
 		ret = PTR_ERR(fsl_dev->pix_clk);
-- 
2.1.0.27.g96db324