[PATCH v2] drm/fsl-dcu: Fix endian issue when using clk_register_divider

[Meng Yi]

>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-
> dcu/fsl_dcu_drm_drv.c
> index 7882387..a590ce8 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> @@ -386,7 +386,8 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
>  	snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix",
> pix_clk_in_name);
>  	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>  			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> -			0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> +			!strcmp(fsl_dev->soc->name, "ls1021a")?24:0, 8,
> +			CLK_DIVIDER_ROUND_CLOSEST, NULL);

Tested-by: Meng Yi <meng.yi at nxp.com>

>  	if (IS_ERR(fsl_dev->pix_clk)) {
>  		dev_err(dev, "failed to register pix clk\n");
>  		ret = PTR_ERR(fsl_dev->pix_clk);
> --
> 2.1.0.27.g96db324