[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #5 from Alex Deucher <alexdeucher at gmail.com> ---
Can you clarify the behavior you are seeing as per my questions in comment 1? 
Is it possible this failure is just random?  I don't see why
drm/amdgpu:impl vgt_flush for VI(V5)
would have any affect on mclk at all.  It's just adding some additional
synchronization packets that mesa may already submit today.

The following are likely the reason the mclk is getting stuck.
[    1.570820] 
                failed to send message 5e ret is 0 
[    1.953147] 
                failed to send pre message 145 ret is 0 

Please use /sys/kernel/debug/dri/64/amdgpu_pm_info to verify the clocks at
runtime rather than the files in sysfs.

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