[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #9 from Alex Deucher <alexdeucher at gmail.com> ---
Created attachment 128166
  --> https://bugs.freedesktop.org/attachment.cgi?id=128166&action=edit
possible fix

Does this patch fix the issue?

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