[PATCH v2 2/2] dt-bindings: drm/bridge: Document Cadence DSI bridge bindings

[Boris Brezillon]

Hi Tomi,

On Tue, 6 Jun 2017 15:30:26 +0300
Tomi Valkeinen <tomi.valkeinen at ti.com> wrote:

> On 02/06/17 15:04, Boris Brezillon wrote:
> > Document the bindings used for the Cadence DSI bridge.
> > 
> > Signed-off-by: Boris Brezillon <boris.brezillon at free-electrons.com>
> > ---
> >  .../bindings/display/bridge/cdns,dsi.txt           | 55 ++++++++++++++++++++++
> >  1 file changed, 55 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
> > new file mode 100644
> > index 000000000000..770c5c5b1e93
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
> > @@ -0,0 +1,55 @@
> > +Cadence DSI bridge
> > +==================
> > +
> > +The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
> > +
> > +Required properties:
> > +- compatible: should be set to "cdns,dsi".
> > +- reg: physical base address and length of the controller's registers.
> > +- interrupts: interrupt line connected to the DSI bridge.
> > +- clocks: DSI bridge clocks.
> > +- clock-names: must contain "pclk" and "sysclk".  
> 
> clock-names doesn't match the example below.

Indeed. I'll fix the example.

> 
> > +- phys: phandle link to the MIPI D-PHY controller.
> > +- phy-names: must contain "dphy".
> > +- #address-cells: must be set to 1.
> > +- #size-cells: must be set to 0.
> > +
> > +Required subnodes:
> > +- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
> > +  Currently contains a single input port at address 0 representing the DPI
> > +  input. Other ports will be added later to support the SDI inputs.  
> 
> Typo with "SDI".

No, the 2nd and 3rd input ports are really called SDI. Here
is the datasheet description:

"
SDI: 
Serial Display Interface - this is the name of the block that is built
to interface the Display application processor to the DSI link. This is
a proprietary interface.
"

Thanks,

Boris