[radeon-alex:raven-hybrid 103/134] drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:375:4-36: duplicated argument to & or | (fwd)

Julia Lawall julia.lawall at lip6.fr
Thu May 11 02:15:36 UTC 2017


Lines 375 and 376 mention the same constant.  Maybe something else was
intended, or mybe line 376 can just be dropped.

julia

---------- Forwarded message ----------
Date: Thu, 11 May 2017 09:07:22 +0800
From: kbuild test robot <fengguang.wu at intel.com>
To: kbuild at 01.org
Cc: Julia Lawall <julia.lawall at lip6.fr>
Subject: [radeon-alex:raven-hybrid 103/134]
    drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:375:4-36: duplicated argument to & or
    |

CC: kbuild-all at 01.org
CC: dri-devel at lists.freedesktop.org
TO: Huang Rui <ray.huang at amd.com>
CC: Alex Deucher <alexander.deucher at amd.com>
CC: Hawking Zhang <Hawking.Zhang at amd.com>

tree:   git://people.freedesktop.org/~agd5f/linux.git raven-hybrid
head:   5b18fa600648660d8df93cbc8a29869cac80780b
commit: fcf6d0bbe8f62d27807b53e5e52678b51f9b9bed [103/134] drm/amdgpu/vcn: add sw clock gating
:::::: branch date: 23 hours ago
:::::: commit date: 29 hours ago

>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c:375:4-36: duplicated argument to & or |

git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git
git remote update radeon-alex
git checkout fcf6d0bbe8f62d27807b53e5e52678b51f9b9bed
vim +375 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

fcf6d0bb Huang Rui 2017-04-20  359  		| UVD_CGC_CTRL__MPRD_MODE_MASK
fcf6d0bb Huang Rui 2017-04-20  360  		| UVD_CGC_CTRL__MPC_MODE_MASK
fcf6d0bb Huang Rui 2017-04-20  361  		| UVD_CGC_CTRL__LBSI_MODE_MASK
fcf6d0bb Huang Rui 2017-04-20  362  		| UVD_CGC_CTRL__LRBBM_MODE_MASK
fcf6d0bb Huang Rui 2017-04-20  363  		| UVD_CGC_CTRL__WCB_MODE_MASK
fcf6d0bb Huang Rui 2017-04-20  364  		| UVD_CGC_CTRL__VCPU_MODE_MASK
fcf6d0bb Huang Rui 2017-04-20  365  		| UVD_CGC_CTRL__SCPU_MODE_MASK);
fcf6d0bb Huang Rui 2017-04-20  366  	WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
fcf6d0bb Huang Rui 2017-04-20  367
fcf6d0bb Huang Rui 2017-04-20  368  	/* turn on */
fcf6d0bb Huang Rui 2017-04-20  369  	data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE));
fcf6d0bb Huang Rui 2017-04-20  370  	data |= (UVD_SUVD_CGC_GATE__SRE_MASK
fcf6d0bb Huang Rui 2017-04-20  371  		| UVD_SUVD_CGC_GATE__SIT_MASK
fcf6d0bb Huang Rui 2017-04-20  372  		| UVD_SUVD_CGC_GATE__SMP_MASK
fcf6d0bb Huang Rui 2017-04-20  373  		| UVD_SUVD_CGC_GATE__SCM_MASK
fcf6d0bb Huang Rui 2017-04-20  374  		| UVD_SUVD_CGC_GATE__SDB_MASK
fcf6d0bb Huang Rui 2017-04-20 @375  		| UVD_SUVD_CGC_GATE__SRE_H264_MASK
fcf6d0bb Huang Rui 2017-04-20  376  		| UVD_SUVD_CGC_GATE__SRE_H264_MASK
fcf6d0bb Huang Rui 2017-04-20  377  		| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
fcf6d0bb Huang Rui 2017-04-20  378  		| UVD_SUVD_CGC_GATE__SIT_H264_MASK
fcf6d0bb Huang Rui 2017-04-20  379  		| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
fcf6d0bb Huang Rui 2017-04-20  380  		| UVD_SUVD_CGC_GATE__SCM_H264_MASK
fcf6d0bb Huang Rui 2017-04-20  381  		| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
fcf6d0bb Huang Rui 2017-04-20  382  		| UVD_SUVD_CGC_GATE__SDB_H264_MASK
fcf6d0bb Huang Rui 2017-04-20  383  		| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK

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