[Bug 102905] [R600] Miscompilation of TGSI to VLIW causes artifacts in Gallium Nine with Crysis2 bump mapping

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=102905

--- Comment #2 from iive at yahoo.com ---
Back when I discovered the bug, glennk suggested that this commit might be
involved:
https://cgit.freedesktop.org/mesa/mesa/commit/?id=acef65503e79ce61a16bdba92462f0ed8a7b52c2

"r600g: fix abs() support on ALU 3 source operands instructions
Since alu does not support abs() modifier on source operands, spill
and apply the modifiers to a temp register when needed."

It turns:
  cndge r0.xy, r1, |r2|, r3   

into:

  mov  r12.x, |r2|
  cndge r0.x, r1, r12, r3
  mov  r12.y, |r2|
  cndge r0.y, r1, r12, r3


This breaks the "cndge" into separate VLIW. 

The problem that causes this bug is when the first half of the above code,
changes the condition check in the second. Something that will not happen, if
"cndge" is executed as a single VLIW.
Aka I have "cndge r0.xy, r0.xx, |r2|, r3" that is turned into:
  mov  r12.x, |r2|
  cndge r0.x, r0.x, r12, r3
  mov  r12.y, |r2|
  cndge r0.y, r0.x, r12, r3

I think that we should copy the whole register first.
The generated code should looks like this:

  mov r12, |r2|
  cndge r0.xy, r1, r12, r3

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