[DPU PATCH 10/11] drm/msm/dpu: correct dpu_io_util.h include path

ryadav at codeaurora.org ryadav at codeaurora.org
Thu May 31 11:41:58 UTC 2018


On 2018-05-30 22:00, Jordan Crouse wrote:
> On Wed, May 30, 2018 at 08:19:47PM +0530, Rajesh Yadav wrote:
>> dpu_io_util.h is moved from standard include path
>> to driver folder, correct the include path in code.
>> 
>> Signed-off-by: Rajesh Yadav <ryadav at codeaurora.org>
> 
> If the previous patch doesn't compile without this fix you should 
> squash them.
Hi Jordan,
Yeah you are right, will squash it in v2.
We are trying to keep msm core and dpu changes in separate patches for 
better squashing when they are pulled by Sean in dpu-staging tree but 
for this instance can't break compilation so yeah I'll squash it with 
previous one.

Thanks,
Rajesh

> 
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 1 -
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 2 +-
>>  2 files changed, 1 insertion(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
>> index 24c3274..f997bd9 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
>> @@ -20,7 +20,6 @@
>>  #include <linux/slab.h>
>>  #include <linux/mutex.h>
>>  #include <linux/of_platform.h>
>> -#include <linux/dpu_io_util.h>
>> 
>>  #include "dpu_power_handle.h"
>>  #include "dpu_trace.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
>> index 9a6d4b9..193f468 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
>> @@ -21,7 +21,7 @@
>>  #define DPU_POWER_HANDLE_ENABLE_BUS_IB_QUOTA	1600000000
>>  #define DPU_POWER_HANDLE_DISABLE_BUS_IB_QUOTA	0
>> 
>> -#include <linux/dpu_io_util.h>
>> +#include "dpu_io_util.h"
>> 
>>  /* event will be triggered before power handler disable */
>>  #define DPU_POWER_EVENT_PRE_DISABLE	0x1


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