[Bug 110674] Crashes / Resets From AMDGPU / Radeon VII

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Sun Aug 11 17:00:25 UTC 2019


--- Comment #71 from Sylvain BERTRAND <sylvain.bertrand at gmail.com> ---
On Sun, Aug 11, 2019 at 01:15:48AM +0000, bugzilla-daemon at freedesktop.org
> I think the clock dysregulation and excessive voltage/wattage are symptoms of

Is there a way to configure the smu block to keep the memory clock to its max
with the appropriate power/voltage? If the smu block do configure some of the
vram arbiter block priority, could we tell it to keep the dc[en]x to max
priority and ignore display vram watermarks? (due to the realtime requirement
of monitor data transmission, I still don't understand the existence of
watermarks in the first place, I would need data which proves me wrong).

On my AMD TAHITI XT, the memory clock seems to be locked to the max (only 1
full hd 144Hz monitor). I recall dce6 has fancy inner-blocks configuration: I
simplified it in my custom driver (something about availability of display
clocks and memory bandwidth. Maybe the smu while clock/power managing breaks
due this dc[en]x "fancy" inner-blocks configuration. 

Additionnally, never heard of 2 displays which would be driven by a common
display block and being in sync. Is the sync dependant on the monitors and not
the display block??  What I am missing ? The nasty displayport mst thingy?
I would always set this to false.

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