[PATCH] drm: include: fix W=1 warnings in struct drm_dsc_config

Manasi Navare manasi.d.navare at intel.com
Tue Sep 10 17:58:07 UTC 2019


On Tue, Sep 10, 2019 at 12:58:24PM +0000, Harry Wentland wrote:
> +Manasi, Gaurav
> 
> On 2019-09-09 9:52 a.m., Benjamin Gaignard wrote:
> > Change scale_increment_interval and nfl_bpg_offset fields to
> > u32 to avoid W=1 warnings because we are testing them against
> > 65535.
> > 
> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard at st.com>
> > ---
> >   include/drm/drm_dsc.h | 6 ++++--
> >   1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> > index 887954cbfc60..e495024e901c 100644
> > --- a/include/drm/drm_dsc.h
> > +++ b/include/drm/drm_dsc.h
> > @@ -207,11 +207,13 @@ struct drm_dsc_config {
> >   	 * Number of group times between incrementing the scale factor value
> >   	 * used at the beginning of a slice.
> >   	 */
> > -	u16 scale_increment_interval;
> > +	u32 scale_increment_interval;
> 
> The DSC spec defines both as u16. I think the check in drm_dsc.c is 
> useless and should be dropped.
>

I agree with Harry here, all these variables should match the number of bits
in the spec, increasing them to u32 allows more values which violates the
DSC spec.

It should stay u16

Manasi
 
> Harry
> 
> > +
> >   	/**
> >   	 * @nfl_bpg_offset: Non first line BPG offset to be used
> >   	 */
> > -	u16 nfl_bpg_offset;
> > +
> > +	u32 nfl_bpg_offset;
> >   	/**
> >   	 * @slice_bpg_offset: BPG offset used to enforce slice bit
> >   	 */
> > 
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