[PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree

[Krzysztof Kozlowski]

On Mon, Oct 26, 2020 at 01:17:05AM +0300, Dmitry Osipenko wrote:
> Add interconnect properties to the Memory Controller, External Memory
> Controller and the Display Controller nodes in order to describe hardware
> interconnection.
> 
> Signed-off-by: Dmitry Osipenko <digetx at gmail.com>
> ---
>  arch/arm/boot/dts/tegra30.dtsi | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index aeae8c092d41..2caf6cc6f4b1 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -210,6 +210,17 @@ dc at 54200000 {
>  
>  			nvidia,head = <0>;
>  
> +			interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,

Does not compile.

> +					<&mc TEGRA30_MC_DISPLAY0B &emc>,
> +					<&mc TEGRA30_MC_DISPLAY1B &emc>,
> +					<&mc TEGRA30_MC_DISPLAY0C &emc>,
> +					<&mc TEGRA30_MC_DISPLAYHC &emc>;
> +			interconnect-names = "wina",
> +					     "winb",
> +					     "winb-vfilter",
> +					     "winc",
> +					     "cursor";
> +
>  			rgb {
>  				status = "disabled";
>  			};
> @@ -229,6 +240,17 @@ dc at 54240000 {
>  
>  			nvidia,head = <1>;
>  
> +			interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
> +					<&mc TEGRA30_MC_DISPLAY0BB &emc>,
> +					<&mc TEGRA30_MC_DISPLAY1BB &emc>,
> +					<&mc TEGRA30_MC_DISPLAY0CB &emc>,
> +					<&mc TEGRA30_MC_DISPLAYHCB &emc>;
> +			interconnect-names = "wina",
> +					     "winb",
> +					     "winb-vfilter",
> +					     "winc",
> +					     "cursor";
> +
>  			rgb {
>  				status = "disabled";
>  			};
> @@ -748,15 +770,18 @@ mc: memory-controller at 7000f000 {
>  
>  		#iommu-cells = <1>;
>  		#reset-cells = <1>;
> +		#interconnect-cells = <1>;
>  	};
>  
> -	memory-controller at 7000f400 {
> +	emc: memory-controller at 7000f400 {
>  		compatible = "nvidia,tegra30-emc";
>  		reg = <0x7000f400 0x400>;
>  		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&tegra_car TEGRA30_CLK_EMC>;
>  
>  		nvidia,memory-controller = <&mc>;
> +

No need for blank line.

Best regards,
Krzysztof

> +		#interconnect-cells = <0>;
>  	};
>  
>  	fuse at 7000f800 {
> -- 
> 2.27.0
>