[PATCH] drm: mxsfb: Support 24-bit SPWG, JEIDA bus formats
Marek Vasut
marex at denx.de
Sun Jul 4 09:53:41 UTC 2021
On 7/4/21 11:38 AM, Jagan Teki wrote:
> 24-bit SPWG, JEIDA bus formats are considered as 24-bit
> bus widths for LCDC_CTRL register in mxsfb.
>
> Add support for it.
>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_kms.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> index 22cb749fc9bc..5657155f9633 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> @@ -85,6 +85,8 @@ static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb,
> ctrl |= CTRL_BUS_WIDTH_18;
> break;
> case MEDIA_BUS_FMT_RGB888_1X24:
> + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
On MX8MM/MN, the bus between LCDIF and DSIM is plain parallel bus, so
this patch is wrong.
You want to pick
drm: mxsfb: Use bus_format from the nearest bridge if present
and then implement .atomic_get_input_bus_fmts on all your bridges. And
only then you will get the correct MEDIA_BUS_FMT_RGB888_1X24 here.
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