[PATCH v3 01/14] drm/i915/gen8: Create separate reg definitions for new MCR registers
Balasubramani Vivekanandan
balasubramani.vivekanandan at intel.com
Mon Oct 17 16:49:13 UTC 2022
On 14.10.2022 16:02, Matt Roper wrote:
> Gen8 was the first time our hardware had multicast registers (or at
> least the first time the multicast nature was exposed and MMIO accesses
> could be steered). There are some registers that transitioned from
> singleton behavior to multicast during the gen7 -> gen8 transition;
> let's duplicate the register definitions for those registers in
> preparation for upcoming patches that will handle MCR registers in a
> special manner.
>
> The registers adjusted are:
> * MISCCPCTL
> * SAMPLER_INSTDONE
> * ROW_INSTDONE
> * ROW_CHICKEN2
> * HALF_SLICE_CHICKEN1
> * HALF_SLICE_CHICKEN3
>
> v2:
> - Use the gen8 version of HALF_SLICE_CHICKEN3 in GVT's gen9 engine MMIO
> list. (Bala)
> - Update to the gen8 version of MISCCPCTL in a couple new workarounds
> that were recently added for DG2/PVC. (Bala)
>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++----------
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 9 ++++---
> 9 files changed, 36 insertions(+), 26 deletions(-)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
Regards,
Bala
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