[PATCH 3/3] drm/i915/mtl: C6 residency and C state type for MTL SAMedia

[Dixit, Ashutosh]

On Mon, 17 Oct 2022 13:12:33 -0700, Dixit, Ashutosh wrote:
>
> On Fri, 14 Oct 2022 20:26:18 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar <badal.nilawar at intel.com>
>
> Hi Badal,
>
> One question below.
>
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 1fb053cbf52db..3a9bb4387248e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -256,6 +256,61 @@ static int ilk_drpc(struct seq_file *m)
> >	return 0;
> >  }
> >
> > +static int mtl_drpc(struct seq_file *m)
> > +{
>
> Here we have:
>
> > +	global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9);
> and
> > +	seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake);
>
> In gen6_drpc we have:
>
>	mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> and
>	seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
>
> Also:
>	#define FORCEWAKE_MT		_MMIO(0xa188)
>	#define FORCEWAKE_GT_GEN9	_MMIO(0xa188)
>
> So they are both the same register. So what is the reason for this
> difference, which one should we use?
>
> Also let's have the prints in the same order as gen6_drpc (move fw request
> before rc6 residency).

This has been made identical to gen6_drpc in series v8.

Thanks.
--
Ashutosh