[PATCH] drm/i915/gt: Mask media GuC interrupts

[Andi Shyti]

MTL features a dedicated media engine that operates on its
independent GT, requiring activation of its specific interrupt
set.

Enable the necessary interrupts in a single action when the media
engine is present, bypassing the need to iterate through all the
GTs.

Signed-off-by: Andi Shyti <andi.shyti at linux.intel.com>
---
Hi,

I'm starting with v0 as this patch is very different from the
ones proposed recently.

After all the discussions on this patch, I took Matt's suggestion
since it seemed the most immediate.

However, in the long run, I agree that we should have a
specific mtl_ function for enabling interrupts.

Thank you Matt and Daniele for your input.

If this patch hasn't missed anything, is it too optimistic to
expect MTL to boot? :-)

Andi

 drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 1b25a60391522..162a27b4c4095 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -254,7 +254,6 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 {
 	struct intel_uncore *uncore = gt->uncore;
 	u32 irqs = GT_RENDER_USER_INTERRUPT;
-	u32 guc_mask = intel_uc_wants_guc(&gt->uc) ? GUC_INTR_GUC2HOST : 0;
 	u32 gsc_mask = 0;
 	u32 dmask;
 	u32 smask;
@@ -309,17 +308,20 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 	if (gsc_mask)
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
 
-	if (guc_mask) {
+	if (intel_uc_wants_guc(&gt->uc)) {
+		u32 guc_mask = GUC_INTR_GUC2HOST;
 		/* the enable bit is common for both GTs but the masks are separate */
-		u32 mask = gt->type == GT_MEDIA ?
-			REG_FIELD_PREP(ENGINE0_MASK, guc_mask) :
-			REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
+		u32 mask = REG_FIELD_PREP(ENGINE1_MASK, guc_mask);
+
+		/* Mask the GuC interrupts of media engine if present */
+		if (MEDIA_VER(gt->i915) >= 13)
+			mask |= REG_FIELD_PREP(ENGINE0_MASK, guc_mask);
 
 		intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE,
 				   REG_FIELD_PREP(ENGINE1_MASK, guc_mask));
 
 		/* we might not be the first GT to write this reg */
-		intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);
+		intel_uncore_write(uncore, MTL_GUC_MGUC_INTR_MASK, mask);
 	}
 
 	/*
-- 
2.39.2