[PATCH 1/2] dt-bindings: display: simple: support non-default data-mapping
Johannes Zink
j.zink at pengutronix.de
Wed Apr 19 06:29:54 UTC 2023
Hi Rob,
On 4/18/23 23:20, Rob Herring wrote:
> On Fri, Apr 14, 2023 at 06:11:15PM +0200, Johannes Zink wrote:
>> Some Displays support more than just a single default lvds data mapping,
>> which can be used to run displays on only 3 LVDS lanes in the jeida-18
>> data-mapping mode.
>>
>> Add an optional data-mapping property, analogously to panel-lvds, to
>> allow overriding the default data mapping.
>>
>> Signed-off-by: Johannes Zink <j.zink at pengutronix.de>
>> ---
>> .../bindings/display/panel/panel-simple.yaml | 51 +++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
>> index 18241f4051d2..6e219f67dd67 100644
>> --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
>> +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
>> @@ -349,6 +349,57 @@ properties:
>> power-supply: true
>> no-hpd: true
>> hpd-gpios: true
>> + data-mapping:
>> + enum:
>> + - jeida-18
>> + - jeida-24
>> + - vesa-24
>> + description: |
>> + The color signals mapping order.
>> +
>> + LVDS data mappings are defined as follows.
>> +
>> + - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
>> + [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
>> +
>> + Slot 0 1 2 3 4 5 6
>> + ________________ _________________
>> + Clock \_______________________/
>> + ______ ______ ______ ______ ______ ______ ______
>> + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>> + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>> + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>> +
>> + - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
>> + specifications. Data are transferred as follows on 4 LVDS lanes.
>> +
>> + Slot 0 1 2 3 4 5 6
>> + ________________ _________________
>> + Clock \_______________________/
>> + ______ ______ ______ ______ ______ ______ ______
>> + DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
>> + DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
>> + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
>> + DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
>> +
>> + - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
>> + Data are transferred as follows on 4 LVDS lanes.
>> +
>> + Slot 0 1 2 3 4 5 6
>> + ________________ _________________
>> + Clock \_______________________/
>> + ______ ______ ______ ______ ______ ______ ______
>> + DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>> + DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>> + DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>> + DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
>> +
>> + Control signals are mapped as follows.
>> +
>> + CTL0: HSync
>> + CTL1: VSync
>> + CTL2: Data Enable
>> + CTL3: 0
>
> Why do you duplicate what's in display/lvds.yaml?
I don't think any of the other properties from display/lvds.yaml
currently make any sense to be put into simple-panel, thus I selectively
picked this one.
If there is a way to selectively pick only the data_mapping, please let
me know and I send a V2
>
> This also just made 'data-mapping' valid on non-LVDS panels.
what is the canonical way of restricting the data-mapping property to
LVDS panels only? Or ist the proper way to go to move the panel I use
(innolux,g101ice-l01) to its own yaml file, include panel-simple.yaml
and leave the others alone? I think other LVDS panels might benefit from
this series though, which is why I think it makes sense to add the
property to all LVDS panels.
Best regards
Johannes
>
> Rob
>
--
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