[PATCH 5/6] drm/msm/dpu: Add hw revision 4.1 (SDM670)
Richard Acayan
mailingradian at gmail.com
Mon Oct 2 21:27:13 UTC 2023
On Mon, Sep 25, 2023 at 07:26:32PM -0400, Richard Acayan wrote:
> The Snapdragon 670 uses similar clocks (with one frequency added) to the
> Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
> with configuration from the Pixel 3a downstream kernel.
>
> Since revision 4.0 is SDM845, reuse some configuration from its catalog
> entry.
>
> Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi
> Signed-off-by: Richard Acayan <mailingradian at gmail.com>
> ---
> .../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 105 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 113 insertions(+)
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> new file mode 100644
> index 000000000000..eaccb16b5db9
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> @@ -0,0 +1,105 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023, Richard Acayan. All rights reserved.
> + */
> +
> +#ifndef _DPU_4_1_SDM670_H
> +#define _DPU_4_1_SDM670_H
> +
> +static const struct dpu_mdp_cfg sdm670_mdp = {
> + .name = "top_0",
> + .base = 0x0, .len = 0x45c,
> + .features = BIT(DPU_MDP_AUDIO_SELECT),
> + .clk_ctrls = {
> + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
> + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
> + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
> + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
> + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8},
> + },
> +};
> +
> +static const struct dpu_sspp_cfg sdm670_sspp[] = {
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1c8,
> + .features = VIG_SDM845_MASK_SDMA,
> + .sblk = &sdm670_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1c8,
> + .features = VIG_SDM845_MASK_SDMA,
> + .sblk = &sdm670_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1c8,
> + .features = DMA_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1c8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1c8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + },
> +};
> +
> +static struct dpu_dsc_cfg sdm670_dsc[] = {
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x140,
> + },
> + {
Let's join these braces on the same line.
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x140,
> + },
> +};
> +
> +static struct dpu_mdss_version sdm670_mdss_ver = {
> + .core_major_ver = 4,
> + .core_minor_ver = 1,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sdm670_cfg = {
> + .mdss_ver = &sdm670_mdss_ver,
> + .caps = &sdm845_dpu_caps,
> + .mdp = &sdm670_mdp,
> + .ctl_count = ARRAY_SIZE(sdm845_ctl),
> + .ctl = sdm845_ctl,
> + .sspp_count = ARRAY_SIZE(sdm670_sspp),
> + .sspp = sdm670_sspp,
> + .mixer_count = ARRAY_SIZE(sdm845_lm),
> + .mixer = sdm845_lm,
> + .pingpong_count = ARRAY_SIZE(sdm845_pp),
> + .pingpong = sdm845_pp,
> + .dsc_count = ARRAY_SIZE(sdm670_dsc),
> + .dsc = sdm670_dsc,
> + .intf_count = ARRAY_SIZE(sdm845_intf),
> + .intf = sdm845_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .perf = &sdm845_perf_data,
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 713dfc079718..63b274ae032a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -313,6 +313,11 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
> .rot_format_list = rotation_v2_formats,
> };
>
> +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_0 =
> + _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED3);
> +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_1 =
> + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3);
> +
> static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
> _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3);
> static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
> @@ -655,6 +660,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
> #include "catalog/dpu_3_0_msm8998.h"
>
> #include "catalog/dpu_4_0_sdm845.h"
> +#include "catalog/dpu_4_1_sdm670.h"
>
> #include "catalog/dpu_5_0_sm8150.h"
> #include "catalog/dpu_5_1_sc8180x.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 6c9634209e9f..dae5a1555e44 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -831,6 +831,7 @@ struct dpu_mdss_cfg {
>
> extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
> extern const struct dpu_mdss_cfg dpu_sdm845_cfg;
> +extern const struct dpu_mdss_cfg dpu_sdm670_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8150_cfg;
> extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index aa6ba2cf4b84..0049fb1de1e8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1362,6 +1362,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
> static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
> { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
> + { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
> { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
> { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
> { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
> --
> 2.42.0
>
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