[PATCH v2 2/2] drm: adv7511: Fix out-of-bounds array in clock_div_by_lanes
Biju Das
biju.das.jz at bp.renesas.com
Wed Nov 6 14:24:23 UTC 2024
Hi Laurent Pinchart,
> -----Original Message-----
> From: dri-devel <dri-devel-bounces at lists.freedesktop.org> On Behalf Of Laurent Pinchart
> Sent: 06 November 2024 13:18
> Subject: Re: [PATCH v2 2/2] drm: adv7511: Fix out-of-bounds array in clock_div_by_lanes
>
> On Wed, Nov 06, 2024 at 10:20:43AM +0000, Biju Das wrote:
> > Hi Laurent Pinchart,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> > > Sent: 05 November 2024 16:06
> > > Subject: Re: [PATCH v2 2/2] drm: adv7511: Fix out-of-bounds array in
> > > clock_div_by_lanes
> > >
> > > Hi Biju,
> > >
> > > Thank you for the patch.
> > >
> > > On Tue, Nov 05, 2024 at 11:12:19AM +0000, Biju Das wrote:
> > > > Fix out-of-bounds array in adv7511_dsi_config_timing_gen(), when
> > > > dsi lanes = 1.
> > >
> > > Does the hardware support using the internal timing generator with a
> > > single lane ? If so
> >
> > As per the binding documentation [1], ADV7535 supports single lane.
> > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tr
> > ee/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml?h
> > =next-20241106
> >
> > > adv7511_dsi_config_timing_gen() should be fixed, otherwise that
> > > should be explained in the commit
> >
> > On RZ/G2L SMARC EVK platform, lanes=2,3,4 works ok, But with setting
> > lanes=1, video is unstable by trying with clock_divider as 6,7 and 8 by updating the array and also
> disabling internal timing generator.
>
> Is that an issue specific to that board, or to the chip in general ? If it's specific to the board,
> disabling 1 lane usage for everybody in the driver isn't the right option.
At this moment, I do not know it is specific to board as with the current code
with lane=1 and internal timing generator, it will lead to kernel crash.
So looks like no one tested lane=1 with internal timing generator.
Then the question is any user has tested lanes=1 by disabling internal generator??
Lane=1 corresponds to resolution 800x600 at 60 and below.
Cheers,
Biju
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