[PATCH V4 21/23] drm/etnaviv: need to disable clock gating when doing profiling

[Lucas Stach]

Am Dienstag, den 12.09.2017, 17:11 +0200 schrieb Christian Gmeiner:
> As done by Vivante kernel driver.

You need to move the VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS from
etnaviv_gpu_update_clock to the GPU init path. Otherwise a thermal
throttling request may disable the debug registers again, while the
profiled commandstream is in flight on the GPU.

Regards,
Lucas

> Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
> Reviewed-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index 842b6642dcd6..04acc3a64c3c 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -1341,6 +1341,13 @@ static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
>  static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
>  	struct etnaviv_event *event)
>  {
> +	u32 val;
> +
> +	/* disable clock gating */
> +	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
> +	val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
> +	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
> +
>  	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
>  }
>  
> @@ -1349,6 +1356,7 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
>  {
>  	const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
>  	unsigned int i;
> +	u32 val;
>  
>  	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
>  
> @@ -1357,6 +1365,11 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
>  
>  		*pmr->bo_vma = pmr->sequence;
>  	}
> +
> +	/* enable clock gating */
> +	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
> +	val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
> +	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
>  }
>  
>