[Freedreno] [PATCH] UNTESTED: drm/msm: enabled a430 support
Craig Stout
cstout at google.com
Fri Dec 4 08:51:24 PST 2015
Hi Rob,
The first time I run it, 'completed fence' is 0.
I don't see any IOMMU faults in the log.
Also, I am cherry-picking drm commits back into the android angler 3.10
kernel, so it's possible I'm missing something important from upstream.
I'll take a look.
On Fri, Dec 4, 2015 at 8:47 AM, Craig Stout <cstout at google.com> wrote:
> Hi Rob,
>
> The first time I run it, 'completed fence' is 0.
>
> I don't see any IOMMU faults in the log.
>
> Also, I am cherry-picking drm commits back into the android angler 3.10
> kernel, so it's possible I'm missing something important from upstream.
> I'll take a look.
>
> -craig
>
>
> On Thu, Dec 3, 2015 at 6:28 PM Rob Clark <robdclark at gmail.com> wrote:
>
>> On Thu, Dec 3, 2015 at 9:01 PM, Craig Stout <cstout at chromium.org> wrote:
>> > With your patch, we do get past a4xx_me_init(). However a simple gl
>> test
>> > (just a gl clear) isn't working. Kernel log shows the following, then
>> the
>> > gpu is restarted.
>> >
>> > [11252.988097] A430: Int status 00000200
>> > [11253.949306] msm qcom,msm_drm_dummy.20: A430: hangcheck detected gpu
>> > lockup!
>> > [11253.955240] msm qcom,msm_drm_dummy.20: A430: completed fence:
>> 1421
>> > [11253.961756] msm qcom,msm_drm_dummy.20: A430: submitted fence:
>> 1422
>>
>> hmm, I don't suppose the first "completed fence" msg was something >0?
>> Which would indicate that at least *some* submits went through..
>>
>> I'll give another try w/ a420 vs a430 cmdstream traces w/ something
>> involving textures.. It's possible the quick 'test-cat' trace I did
>> wasn't sufficient to notice some difference.
>>
>> Did you get any iommu fault msgs, by any chance?
>>
>> The other case is that we need to look closer at the clks and
>> regulators, I think. When adding a306, I did have to add a new clk
>> (in that case, alt_mem_iface_clk.. see
>> de558cd2ae2e9999d0b6328c22c398ff85b6327c). Could be the same sort of
>> situation w/ a430.
>>
>> Beyond that, in downstream driver, a430 has the additional feature
>> flags, compared to a420:
>>
>> ADRENO_CONTENT_PROTECTION - basically looks like it sets a flag
>> used by one of the gpu iommu's for secure-context.. maybe we need to
>> do something there?
>> ADRENO_PPD (peak power detect) and ADRENO_SPTP_PC (SP/TP hw
>> controlled power collapse).. from the looks of it so far, we can
>> ignore these if we don't enable ST/TP power collapse. Might not be a
>> bad idea to start out by underclocking the gpu to rule out
>> power/thermal issues.
>>
>> BR,
>> -R
>>
>> > On Thu, Dec 3, 2015 at 1:20 PM, Rob Clark <robdclark at gmail.com> wrote:
>> >>
>> >> Note: temporary hack to avoid regenerating the autogenerated register
>> >> headers, which would likely be conflict-y depending on what kernel you
>> >> are based on.
>> >>
>> >> If you get past a4xx_me_init() without any timeout msgs, that is a good
>> >> sign that the gpu is alive.
>> >>
>> >> In theory, this should be all we need for userspace:
>> >>
>> >> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
>> >> b/src/gallium/drivers/freedreno/freedreno_screen.c
>> >> index 5bbe401..97c4edd 100644
>> >> --- a/src/gallium/drivers/freedreno/freedreno_screen.c
>> >> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c
>> >> @@ -555,6 +555,7 @@ fd_screen_create(struct fd_device *dev)
>> >> fd3_screen_init(pscreen);
>> >> break;
>> >> case 420:
>> >> + case 430:
>> >> fd4_screen_init(pscreen);
>> >> break;
>> >> default:
>> >>
>> >> ---
>> >> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 28
>> >> ++++++++++++++++++++++++++--
>> >> drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++++
>> >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
>> >> 3 files changed, 39 insertions(+), 2 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>> >> b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>> >> index a53f1be..b00e69e 100644
>> >> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>> >> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>> >> @@ -15,6 +15,11 @@
>> >> # include <soc/qcom/ocmem.h>
>> >> #endif
>> >>
>> >> +// XXX temp hack until rnndb updated and a4xx.xml.h regenerated:
>> >> +#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x1b8
>> >> +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x99
>> >> +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x9a
>> >> +
>> >> #define A4XX_INT0_MASK \
>> >> (A4XX_INT0_RBBM_AHB_ERROR | \
>> >> A4XX_INT0_RBBM_ATB_BUS_OVERFLOW | \
>> >> @@ -141,7 +146,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
>> >> uint32_t *ptr, len;
>> >> int i, ret;
>> >>
>> >> - if (adreno_is_a4xx(adreno_gpu)) {
>> >> + if (adreno_is_a420(adreno_gpu)) {
>> >> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);
>> >> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF,
>> 0x000000A4);
>> >> gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN,
>> >> 0x00000001);
>> >> @@ -150,6 +155,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
>> >> gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0,
>> 0x18181818);
>> >> gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1,
>> 0x00000018);
>> >> gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB,
>> >> 0x00000003);
>> >> + } else if (adreno_is_a430(adreno_gpu)) {
>> >> + gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN,
>> >> 0x00000001);
>> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0,
>> 0x18181818);
>> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1,
>> 0x00000018);
>> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0,
>> 0x18181818);
>> >> + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1,
>> 0x00000018);
>> >> + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB,
>> >> 0x00000003);
>> >> } else {
>> >> BUG();
>> >> }
>> >> @@ -160,8 +172,11 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
>> >> /* Tune the hystersis counters for SP and CP idle detection */
>> >> gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10);
>> >> gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
>> >> + if (adreno_is_a430(adreno_gpu)) {
>> >> + gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2,
>> 0x30);
>> >> + }
>> >>
>> >> - /* Enable the RBBM error reporting bits */
>> >> + /* Enable the RBBM error reporting bits */
>> >> gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);
>> >>
>> >> /* Enable AHB error reporting*/
>> >> @@ -190,6 +205,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
>> >> gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) |
>> >> (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));
>> >>
>> >> + /* On A430 enable SP regfile sleep for power savings */
>> >> + /* TODO downstream does this for !420, so maybe applies for 405
>> >> too? */
>> >> + if (!adreno_is_a420(adreno_gpu)) {
>> >> + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,
>> >> + 0x00000441);
>> >> + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,
>> >> + 0x00000441);
>> >> + }
>> >> +
>> >> a4xx_enable_hwcg(gpu);
>> >>
>> >> /*
>> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
>> >> b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> >> index 1ea2df5..43d5aaa 100644
>> >> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
>> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
>> >> @@ -73,6 +73,14 @@ static const struct adreno_info gpulist[] = {
>> >> .pfpfw = "a420_pfp.fw",
>> >> .gmem = (SZ_1M + SZ_512K),
>> >> .init = a4xx_gpu_init,
>> >> + }, {
>> >> + .rev = ADRENO_REV(4, 3, 0, ANY_ID),
>> >> + .revn = 430,
>> >> + .name = "A430",
>> >> + .pm4fw = "a420_pm4.fw",
>> >> + .pfpfw = "a420_pfp.fw",
>> >> + .gmem = (SZ_1M + SZ_512K),
>> >> + .init = a4xx_gpu_init,
>> >> },
>> >> };
>> >>
>> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> >> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> >> index 0a312e9..8db0055 100644
>> >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> >> @@ -228,6 +228,11 @@ static inline int adreno_is_a420(struct adreno_gpu
>> >> *gpu)
>> >> return gpu->revn == 420;
>> >> }
>> >>
>> >> +static inline int adreno_is_a430(struct adreno_gpu *gpu)
>> >> +{
>> >> + return gpu->revn == 430;
>> >> +}
>> >> +
>> >> int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t
>> >> *value);
>> >> int adreno_hw_init(struct msm_gpu *gpu);
>> >> uint32_t adreno_last_fence(struct msm_gpu *gpu);
>> >> --
>> >> 2.5.0
>> >>
>> >
>>
>
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