[igt-dev] [PATCH i-g-t 09/10] lib/i915: add mmio base for engines

[Lionel Landwerlin]

Useful when you want to work with MI_ALU and general purpose registers
local to an engine.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 lib/i915/gem_engine_topology.c | 74 ++++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  5 +++
 2 files changed, 79 insertions(+)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 790d455f..925fdb51 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -22,6 +22,7 @@
  */
 
 #include "drmtest.h"
+#include "intel_chipset.h"
 #include "ioctl_wrappers.h"
 
 #include "i915/gem_engine_topology.h"
@@ -337,3 +338,76 @@ bool gem_engine_is_equal(const struct intel_execution_engine2 *e1,
 {
 	return e1->class == e2->class && e1->instance == e2->instance;
 }
+
+uint32_t intel_get_engine_mmio_base(const uint16_t devid,
+				    const struct intel_execution_engine2 *e)
+{
+	switch (e->class) {
+	case I915_ENGINE_CLASS_RENDER:
+		return 0x2000;
+	case I915_ENGINE_CLASS_COPY:
+		return 0x22000;
+	case I915_ENGINE_CLASS_VIDEO: {
+		uint32_t gen11_bases[] = {
+			0x1c0000,
+			0x1c4000,
+			0x1d0000,
+			0x1d4000,
+		};
+		uint32_t gen8_bases[] = {
+			0x12000,
+			0x1c000,
+		};
+		uint32_t gen6_bases[] = {
+			0x12000,
+		};
+		uint32_t gen4_bases[] = {
+			0x4000,
+		};
+		uint32_t *bases, len = 0;
+
+		if (AT_LEAST_GEN(devid, 11)) {
+			bases = gen11_bases;
+			len = ARRAY_SIZE(gen11_bases);
+		} else if (AT_LEAST_GEN(devid, 8)) {
+			bases = gen8_bases;
+			len = ARRAY_SIZE(gen8_bases);
+		} else if (AT_LEAST_GEN(devid, 6)) {
+			bases = gen6_bases;
+			len = ARRAY_SIZE(gen6_bases);
+		} else if (AT_LEAST_GEN(devid, 4)) {
+			bases = gen4_bases;
+			len = ARRAY_SIZE(gen4_bases);
+		}
+
+		if (e->instance >= len)
+			igt_assert(!"Invalid vcs instance");
+		return bases[e->instance];
+	}
+	case I915_ENGINE_CLASS_VIDEO_ENHANCE: {
+		uint32_t gen11_bases[] = {
+			0x1c8000,
+			0x1d8000,
+		};
+		uint32_t gen7_bases[] = {
+			0x1a000,
+		};
+		uint32_t *bases, len = 0;
+
+		if (AT_LEAST_GEN(devid, 11)) {
+			bases = gen11_bases;
+			len = ARRAY_SIZE(gen11_bases);
+		} else if (AT_LEAST_GEN(devid, 7)) {
+			bases = gen7_bases;
+			len = ARRAY_SIZE(gen7_bases);
+		}
+
+		if (e->instance >= len)
+			igt_assert(!"Invalid vcs instance");
+		return bases[e->instance];
+	}
+
+	default:
+		igt_assert(!"Invalid engine class");
+	}
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index d98773e0..71ce81de 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -27,6 +27,8 @@
 #include "igt_gt.h"
 #include "i915_drm.h"
 
+struct intel_device_info;
+
 #define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
 
 struct intel_engine_data {
@@ -46,6 +48,9 @@ intel_get_current_engine(struct intel_engine_data *ed);
 struct intel_execution_engine2 *
 intel_get_current_physical_engine(struct intel_engine_data *ed);
 
+uint32_t intel_get_engine_mmio_base(const uint16_t devid,
+				    const struct intel_execution_engine2 *e);
+
 void intel_next_engine(struct intel_engine_data *ed);
 
 int gem_context_lookup_engine(int fd, uint64_t engine, uint32_t ctx_id,
-- 
2.24.0