[PATCH] Fix CAT error by adjusting prefetch size for Xe2

[Jagmeet Randhawa]

Due to batch pre-fetch being quite aggressive on Xe2, we need
an extra 4K page at the end of the batch to ensure HW doesn't
pre-fetch beyond the boundaries of the batch itself, hitting
an invalid ppGTT page, resulting in CAT errors. Fix this by
accounting for the xe_cs_prefetch_size() when calculating
the size of the batch.

Suggested-by: Matthew Auld <matthew.auld at intel.com>
Signed-off-by: Jagmeet Randhawa <jagmeet.randhawa at intel.com>
---
 tests/intel/xe_exec_store.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 2e4f57b47..bed118688 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -201,7 +201,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci,
 	uint32_t *batch_map;
 	size_t bo_size = 4096;
 
-	bo_size = ALIGN(bo_size, xe_get_default_alignment(fd));
+	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
 	vm = xe_vm_create(fd, 0, 0);
 	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
 	exec_queues = xe_exec_queue_create(fd, vm, eci, 0);
-- 
2.25.1