[PATCH v3 2/4] lib/amdgpu: add func to read the userqueue support

[Sunil Khatri]

The function asic_userq_readiness read the userq_ip_mask
value set by the kernel which says which ip supports
userqueues on this asic.

Cc: Prosyak, Vitaly <Vitaly.Prosyak at amd.com>
Cc: Jesse Zhang <jesse.zhang at amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri at amd.com>
---
 lib/amdgpu/amd_ip_blocks.c | 17 +++++++++++++++++
 lib/amdgpu/amd_ip_blocks.h |  2 ++
 2 files changed, 19 insertions(+)

diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
index d6764194d..b8227ba2b 100644
--- a/lib/amdgpu/amd_ip_blocks.c
+++ b/lib/amdgpu/amd_ip_blocks.c
@@ -976,6 +976,23 @@ is_rings_available(amdgpu_device_handle device_handle, uint32_t mask,
 	return  hw_ip_info.available_rings & mask;
 }
 
+void asic_userq_readiness(amdgpu_device_handle device_handle, bool arr[AMD_IP_MAX])
+{
+	int r, i;
+	enum amd_ip_block_type ip;
+	struct drm_amdgpu_info_device dev_info = {0};
+
+	r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
+			      sizeof(dev_info), &dev_info);
+	igt_assert_eq(r, 0);
+
+	if (!dev_info.userq_ip_mask)
+		return;
+
+	for (i = 0, ip = AMD_IP_GFX; ip < AMD_IP_MAX; ip++)
+		arr[i++] = dev_info.userq_ip_mask & (1 << ip);
+}
+
 /**
  * asic_rings_readness:
  * @device handle: handle to driver internal information
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 7d48f9107..3c2ecd1ba 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -268,6 +268,8 @@ amdgpu_open_devices(bool open_render_node, int max_cards_supported, int drm_amdg
 void
 asic_rings_readness(amdgpu_device_handle device_handle, uint32_t mask, bool arr[AMD_IP_MAX]);
 
+void asic_userq_readiness(amdgpu_device_handle device_handle, bool arr[AMD_IP_MAX]);
+
 bool
 is_reset_enable(enum amd_ip_block_type ip_type, uint32_t reset_type, const struct pci_addr *pci);
 
-- 
2.43.0