[PATCH v3 3/4] tests/amdgpu: execute userq tests only if userq support IP

[Sunil Khatri]

check the IP supported by userqueues before executing any
userq test cases.

Cc: Prosyak, Vitaly <Vitaly.Prosyak at amd.com>
Cc: Jesse Zhang <jesse.zhang at amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri at amd.com>
---
 tests/amdgpu/amd_basic.c    | 10 +++++-----
 tests/amdgpu/amd_cs_nop.c   | 11 +++--------
 tests/amdgpu/amd_security.c | 13 +++++++++----
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c
index eb8447220..e0029f582 100644
--- a/tests/amdgpu/amd_basic.c
+++ b/tests/amdgpu/amd_basic.c
@@ -697,6 +697,7 @@ igt_main
 	int fd = -1;
 	int r;
 	bool arr_cap[AMD_IP_MAX] = {0};
+	bool userq_arr_cap[AMD_IP_MAX] = {0};
 
 	igt_fixture {
 		uint32_t major, minor;
@@ -717,6 +718,7 @@ igt_main
 		r = setup_amdgpu_ip_blocks(major, minor,  &gpu_info, device);
 		igt_assert_eq(r, 0);
 		asic_rings_readness(device, 1, arr_cap);
+		asic_userq_readiness(device, userq_arr_cap);
 	}
 	igt_describe("Check-alloc-free-VRAM-visible-non-visible-GART-write-combined-cached");
 	igt_subtest("memory-alloc")
@@ -789,12 +791,10 @@ igt_main
 	}
 
 #ifdef AMDGPU_USERQ_ENABLED
-	arr_cap[AMD_IP_GFX] = 1;
-	arr_cap[AMD_IP_COMPUTE] = 1;
 
 	igt_describe("Check-GFX-CS-for-every-available-ring-works-for-write-const-fill-and-copy-operation-using-more-than-one-IB-and-shared-IB");
 	igt_subtest_with_dynamic("cs-gfx-with-IP-GFX-UMQ") {
-		if (arr_cap[AMD_IP_GFX]) {
+		if (userq_arr_cap[AMD_IP_GFX]) {
 			igt_dynamic_f("cs-gfx-with-umq")
 			amdgpu_command_submission_gfx(device, info.hw_ip_version_major < 11, true);
 		}
@@ -802,7 +802,7 @@ igt_main
 
 	igt_describe("Check-COMPUTE-CS-for-every-available-ring-works-for-write-const-fill-copy-and-nop-operation");
 	igt_subtest_with_dynamic("cs-compute-with-IP-COMPUTE-UMQ") {
-		if (arr_cap[AMD_IP_COMPUTE]) {
+		if (userq_arr_cap[AMD_IP_COMPUTE]) {
 			igt_dynamic_f("cs-compute-with-umq")
 			amdgpu_command_submission_compute(device, true);
 		}
@@ -810,7 +810,7 @@ igt_main
 
 	igt_describe("Check-sync-dependency-using-GFX-ring");
 	igt_subtest_with_dynamic("sync-dependency-test-with-IP-GFX-UMQ") {
-		if (arr_cap[AMD_IP_GFX]) {
+		if (userq_arr_cap[AMD_IP_GFX]) {
 			igt_dynamic_f("sync-dependency-test-with-umq")
 			amdgpu_sync_dependency_test(device, true);
 		}
diff --git a/tests/amdgpu/amd_cs_nop.c b/tests/amdgpu/amd_cs_nop.c
index 67bb0419d..160c4f026 100644
--- a/tests/amdgpu/amd_cs_nop.c
+++ b/tests/amdgpu/amd_cs_nop.c
@@ -169,6 +169,7 @@ igt_main
 	}, *e;
 	int fd = -1;
 	bool arr_cap[AMD_IP_MAX] = {0};
+	bool userq_arr_cap[AMD_IP_MAX] = {0};
 
 	igt_fixture {
 		uint32_t major, minor;
@@ -182,6 +183,7 @@ igt_main
 		err = amdgpu_cs_ctx_create(device, &context);
 		igt_assert_eq(err, 0);
 		asic_rings_readness(device, 1, arr_cap);
+		asic_userq_readiness(device, userq_arr_cap);
 	}
 
 	for (p = phase; p->name; p++) {
@@ -198,18 +200,11 @@ igt_main
 	}
 
 #ifdef AMDGPU_USERQ_ENABLED
-	/*
-	 * TODO: Add a programmatic check to determine which IPs (gfx, compute, sdma)
-	 * are present for the user-mode queue and execute the test accordingly.
-	 */
-	arr_cap[AMDGPU_HW_IP_GFX] = 1;
-	arr_cap[AMDGPU_HW_IP_COMPUTE] = 1;
-
 	for (p = phase; p->name; p++) {
 		for (e = engines; e->name; e++) {
 			igt_describe("Stressful-and-multiple-cs-of-nop-operations-using-multiple-processes-with-the-same-GPU-context-UMQ");
 			igt_subtest_with_dynamic_f("cs-nops-with-%s-%s0-with-UQ-Submission", p->name, e->name) {
-				if (arr_cap[e->ip_type]) {
+				if (userq_arr_cap[e->ip_type]) {
 					igt_dynamic_f("cs-nop-with-%s-%s0-with-UQ-Submission", p->name, e->name)
 					nop_cs(device, context, e->name, e->ip_type, 0, 20,
 					       p->flags, 1);
diff --git a/tests/amdgpu/amd_security.c b/tests/amdgpu/amd_security.c
index 1c880c11f..ff22fd8db 100644
--- a/tests/amdgpu/amd_security.c
+++ b/tests/amdgpu/amd_security.c
@@ -315,6 +315,7 @@ igt_main
 	struct drm_amdgpu_info_hw_ip  sdma_info = {};
 	int r, fd = -1;
 	bool is_secure = true;
+	bool userq_arr_cap[AMD_IP_MAX] = {0};
 
 	igt_fixture {
 		uint32_t major, minor;
@@ -331,6 +332,7 @@ igt_main
 		igt_assert_eq(r, 0);
 		r = amdgpu_query_hw_ip_info(device, AMDGPU_HW_IP_DMA, 0, &sdma_info);
 		igt_assert_eq(r, 0);
+		asic_userq_readiness(device, userq_arr_cap);
 		igt_skip_on(!is_security_tests_enable(device, &gpu_info, major, minor));
 	}
 
@@ -355,15 +357,18 @@ igt_main
 			AMDGPU_HW_IP_DMA), is_secure);
 
 #ifdef AMDGPU_USERQ_ENABLED
+
 	igt_describe("amdgpu gfx command submission write linear helper with user queue");
 	igt_subtest("gfx-write-linear-helper-secure-umq")
-	amdgpu_command_submission_write_linear_helper(device,
-			get_ip_block(device, AMDGPU_HW_IP_GFX), is_secure, true);
+	if (userq_arr_cap[AMD_IP_GFX])
+		amdgpu_command_submission_write_linear_helper(device,
+				get_ip_block(device, AMDGPU_HW_IP_GFX), is_secure, true);
 
 	igt_describe("amdgpu compute command submission write linear helper with user queue");
 	igt_subtest("compute-write-linear-helper-secure-umq")
-	amdgpu_command_submission_write_linear_helper(device,
-			get_ip_block(device, AMDGPU_HW_IP_COMPUTE), is_secure, true);
+	if (userq_arr_cap[AMD_IP_COMPUTE])
+		amdgpu_command_submission_write_linear_helper(device,
+				get_ip_block(device, AMDGPU_HW_IP_COMPUTE), is_secure, true);
 #endif
 
 	igt_fixture {
-- 
2.43.0