[PATCH v3 14/19] lib/amdgpu: use right API to get the correct size

[Sunil Khatri]

Use amdgpu_query_uq_fw_area_info api to get the
sizes and alignment for shadow and csa.

Signed-off-by: Sunil Khatri <sunil.khatri at amd.com>
---
 lib/amdgpu/amd_ip_blocks.h  |  2 +-
 lib/amdgpu/amd_user_queue.c | 21 ++++++++++-----------
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index e085f1618..231098eb8 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -175,7 +175,7 @@ struct amdgpu_ring_context {
 	uint64_t point;
 	bool user_queue;
 
-	struct drm_amdgpu_info_device dev_info;
+	struct drm_amdgpu_info_uq_fw_areas info;
 };
 
 
diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c
index 1bfc86949..d1763f5d6 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -189,13 +189,13 @@ void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu
 	case AMD_IP_GFX:
 		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
 					    ctxt->csa.va_handle,
-					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
+					    ctxt->csa.mc_addr, ctxt->info.gfx.csa_size,
 					    ctxt->timeline_syncobj_handle, ++ctxt->point,
 					    0, 0);
 
 		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->shadow.handle,
 					    ctxt->shadow.va_handle,
-					    ctxt->shadow.mc_addr, ctxt->dev_info.shadow_size,
+					    ctxt->shadow.mc_addr, ctxt->info.gfx.shadow_size,
 					    ctxt->timeline_syncobj_handle, ++ctxt->point,
 					    0, 0);
 
@@ -219,7 +219,7 @@ void amdgpu_user_queue_destroy(amdgpu_device_handle device_handle, struct amdgpu
 	case AMD_IP_DMA:
 		amdgpu_bo_unmap_and_free_uq(device_handle, ctxt->csa.handle,
 					    ctxt->csa.va_handle,
-					    ctxt->csa.mc_addr, ctxt->dev_info.csa_size,
+					    ctxt->csa.mc_addr, ctxt->info.gfx.csa_size,
 					    ctxt->timeline_syncobj_handle, ++ctxt->point,
 					    0, 0);
 
@@ -268,8 +268,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 		return;
 	}
 
-	r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
-			      sizeof(ctxt->dev_info), &ctxt->dev_info);
+	r = amdgpu_query_uq_fw_area_info(device_handle, AMD_IP_GFX, 0, &ctxt->info);
 	igt_assert_eq(r, 0);
 
 	r = amdgpu_cs_create_syncobj2(device_handle, 0, &ctxt->timeline_syncobj_handle);
@@ -307,8 +306,8 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 
 	switch (type) {
 	case AMD_IP_GFX:
-		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.shadow_size,
-					       ctxt->dev_info.shadow_alignment,
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->info.gfx.shadow_size,
+					       ctxt->info.gfx.shadow_alignment,
 					       AMDGPU_GEM_DOMAIN_GTT,
 					       gtt_flags,
 					       AMDGPU_VM_MTYPE_UC,
@@ -317,8 +316,8 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 					       ctxt->timeline_syncobj_handle, ++ctxt->point);
 		igt_assert_eq(r, 0);
 
-		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
-					       ctxt->dev_info.csa_alignment,
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->info.gfx.csa_size,
+					       ctxt->info.gfx.csa_alignment,
 					       AMDGPU_GEM_DOMAIN_GTT,
 					       gtt_flags,
 					       AMDGPU_VM_MTYPE_UC,
@@ -347,8 +346,8 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
 		break;
 
 	case AMD_IP_DMA:
-		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->dev_info.csa_size,
-					       ctxt->dev_info.csa_alignment,
+		r = amdgpu_bo_alloc_and_map_uq(device_handle, ctxt->info.gfx.csa_size,
+					       ctxt->info.gfx.csa_alignment,
 					       AMDGPU_GEM_DOMAIN_GTT,
 					       gtt_flags,
 					       AMDGPU_VM_MTYPE_UC,
-- 
2.43.0