[Bug 86161] New: Calculation result with only uniform inputs uses too much register space

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=86161

            Bug ID: 86161
           Summary: Calculation result with only uniform inputs uses too
                    much register space
           Product: Mesa
           Version: git
          Hardware: Other
                OS: All
            Status: NEW
          Severity: normal
          Priority: medium
         Component: Drivers/DRI/i965
          Assignee: idr at freedesktop.org
          Reporter: petri.latvala at intel.com
        QA Contact: intel-3d-bugs at lists.freedesktop.org

uniform float ux;
uniform float uy;

void main()
{
  float x = ux * uy;
  gl_FragColor = vec4(x * 0.5);
}



This fragment shader yields the following assembly:

SIMD8 shader: 7 instructions. Compacted 112 to 80 bytes (29%)
   START B0
   (assign  (xyzw) (var_ref gl_FragColor)  (swiz xxxx (expression float *
(expression float * (var_ref ux) (var_ref uy) ) (constant float (0.500000)) )
)) 
mul(8)          g3<1>F          g2<0,1,0>F      g2.1<0,1,0>F    { align1 1Q
compacted };
mul(8)          g4<1>F          g3<8,8,1>F      0.5F            { align1 1Q };
   FB write target 0
mov(8)          g113<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
mov(8)          g114<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
mov(8)          g115<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
mov(8)          g116<1>F        g4<8,8,1>F                      { align1 1Q
compacted };
nop                                                             ;
sendc(8)        null            g113<8,8,1>F
                            render RT write SIMD8 LastRT Surface = 0 mlen 4
rlen 0 { align1 1Q EOT };
   END B0


In particular, the first instruction:
mul(8)          g3<1>F          g2<0,1,0>F      g2.1<0,1,0>F    { align1 1Q
compacted };

The operands are the two uniform values in subregisters g2.0 and g2.1. The
written register region is the whole g3 with exec size 8, where a single float
with exec size 1 would suffice.

Of course just changing the above instruction to exec size 1 would achieve
nothing if the register allocator is not improved to benefit from the leftover
space...

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