[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #20 from Iago Toral <itoral at igalia.com> ---
Connor, I have a question about the code we generate for the double unpack x/y
opcodes, which looks like this (in SIMD8):

mov(8)   g2<1>UD    g18.1<8,4,2>UD   { align1 1Q };
mov(8)   g28<2>UD   g18<8,4,2>UD     { align1 1Q };

Each of these instructions is intended to copy 4 UD elements from the source
the destination, however, the execution size of the instructions is set to 8,
not 4, which means that we have a a vertical dimension of 2 and we we are
actually operating on more data elements than we need. Shouldn't these two
instructions have an execution size of 4 instead?

The thing is that I tried to set the execution size to 4 (this also requires
that I set force_writemask_all to true) but that produces GPU hangs and some
regressions in the fp64 tests, so I guess I am missing something here...

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