[Bug 92788] [IVB/HSW/BYT/BDW/BSW Bisected ]SynMark2 "OglShMapPcf" cannot run as image validation failed

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92788

            Bug ID: 92788
           Summary: [IVB/HSW/BYT/BDW/BSW Bisected ]SynMark2 "OglShMapPcf"
                    cannot run as image validation failed
           Product: Mesa
           Version: unspecified
          Hardware: All
                OS: Linux (All)
            Status: NEW
          Severity: major
          Priority: high
         Component: Drivers/DRI/i965
          Assignee: idr at freedesktop.org
          Reporter: yex.tian at intel.com
        QA Contact: intel-3d-bugs at lists.freedesktop.org
                CC: cwabbott0 at gmail.com, eero.t.tamminen at intel.com

Created attachment 119367
  --> https://bugs.freedesktop.org/attachment.cgi?id=119367&action=edit
Xorg.0.log

System Environment:       
Platform: IVB/HSW/BYT/BDW/BSW
Mesa:    (master)b639ed2f1b170d1184c6d94c88c826c51ffc8726
Kernel: (drm-intel-nightly)d4f412886ec9694658ab17092c3f70569a0405f9

Bug detailed description:
--------------------------------------------------
SynMark2 "OglShMapPcf" cannot run as image validation failed.
It’s Mesa regression,by bisected, show the first bad mesa commit is 486268b.

commit 486268bdb03a36faf09d84e0458ff49dd1325c40 
Author:     Connor Abbott <cwabbott0 at gmail.com>
AuthorDate: Sat Jun 6 13:32:21 2015 -0400
Commit:     Connor Abbott <cwabbott0 at gmail.com>
CommitDate: Fri Oct 30 02:19:00 2015 -0400

    i965: always run the post-RA scheduler

    Before, we would only do scheduling after register allocation if we
    spilled, despite the fact that the pre-RA scheduler was only supposed to
    be for register pressure and set the latencies of every instruction to
    1. This meant that unless we spilled, which we rarely do, then we never
    considered instruction latencies at all, and we usually never bothered
    to try and hide texture fetch latency. Although a later commit removes
    the setting the latency to 1 part, we still want to always run the
    post-RA scheduler since it's able to take the false dependencies that
    the register allocator creates into account, and it can be more
    aggressive than the pre-RA scheduler since it doesn't have to worry
    about register pressure at all.


Please see Xrog.

Reproduce steps:
----------------------------
1, xinit& 
2, ./synmark2 OglShMapPcf

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