[Bug 91926] [SKL bisected] texsubimage pbo intermittent failures

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https://bugs.freedesktop.org/show_bug.cgi?id=91926

--- Comment #35 from Topi Pohjolainen <topi.pohjolainen at intel.com> ---
(In reply to Topi Pohjolainen from comment #34)
> (In reply to Topi Pohjolainen from comment #13)
> > I was able to narrow down the combination of _mesa_update_state() and
> > brw_emit_mi_flush(). I got it simplified to a call _mesa_update_texture()
> > followed by part of the logic in brw_context.c:intel_update_state() - namely
> > calling brw_render_cache_set_check_flush() at least once. That call in turn
> > is simple check for existence of the underlying buffer object of the texture
> > and then a call to brw_emit_mi_flush().
> > 
> > So, after more simplification, I found out that if I'm calling
> > brw_emit_mi_flush() _twice_ after the call for _mesa_meta_pbo_TexSubImage()
> > in intelTexSubImage() I'm not able to reproduce the error. Recall that
> > calling brw_emit_mi_flush() isn't enough.
> > 
> > This is turn means that I'm mostly likely in square one - I'm simple
> > changing the dynamics enough to hide the real bug.
> 
> I have a little more to add here. I started reading bspec again regarding
> flushing and related pipe control options. I added another
> brw_emit_pipe_control_flush() into brw_emit_mi_flush() in order to
> experiment with individual bits of the pipe control command. (All that
> brw_emit_mi_flush() does is to emit pipe-control commands).
> 
> Neither on IVB or on SKL I cannot see any failures if I just submit another
> pipe-control command with only a single bit set, namely
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE. Any other bit didn't seem to make any
> difference.

And here it should be noted that the preceding (and already existing
pipe-control command) in brw_emit_mi_flush() contains this bit among others.

Also I noticed bspec telling me that on SKL TEXTURE_CACHE_INVALIDATE must
always be accompanied with CS_STALL bit. I didn't have it, but the command
still made a difference.

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