[Bug 91926] [SKL bisected] texsubimage pbo intermittent failures

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=91926

--- Comment #42 from Topi Pohjolainen <topi.pohjolainen at intel.com> ---
(In reply to Topi Pohjolainen from comment #39)
> In workarounds I found the following:
> 
> "For Gen6 and Gen7, any time a pipeline flush is used it needs to be
>  followed by eight (8) separate storeDW commands. This is done as a
>  workaround to a known issue where the pipeline flush does not push all
>  cycles to the "GO" point. The storeDWs will not accomplish this process
>  but will create enough stall time to ensure all cycles are at GO prior
>  to execution of the next buffer or part of the buffer. This is required
>  for producer/consumer model."
> 
> I don't exactly know to what "storeDW" refers here and I added in
> brw_emit_mi_flush() after the flush:
> 
>    for (unsigned i = 0; i < 8; ++i) 
>       brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
>                                   brw->workaround_bo, 0, 0, 0);
> 
> (which writes in fact 8 times qwords).
> 
> This at least doesn't make any difference either on IVB or SKL.

Also just tried using MI_STORE_DATA_IMM instead of pipe control command -
doesn't help on IVB.

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