[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #48 from Iago Toral <itoral at igalia.com> ---
Connor, I think there is a problem with the implementation of d2f and f2d in
the vec4 backend. These use a generator opcode that switches to scalar mode
like this (for d2f):

brw_set_default_access_mode(p, BRW_ALIGN_1);
dst.hstride = BRW_HORIZONTAL_STRIDE_2;
dst.width = BRW_WIDTH_4;
brw_MOV(p, dst, src[0]);
brw_set_default_access_mode(p, BRW_ALIGN_16);

The problem with this is that scalar mode does not consider the swizzle in
src[0] and because of copy-propagation, we can end up with a swizzle like zwzw
here.

In the case of d2f, it seems that  I can just do a normal MOV in align16 mode
and that seems to work, but f2d is not so easy and we probably need align1 mode
there.

Of course, we can fix this by disabling copy-propagation for the generator
opcodes we use for this, I suppose that should be alright, but I wonder if you
think there is a better approach.

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