[Bug 92760] Add FP64 support to the i965 shader backends

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Mon Feb 15 10:48:40 UTC 2016


https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #51 from Iago Toral <itoral at igalia.com> ---
I noticed that nir_lower_locals_to_regs can insert MOVs of 64-bit things and we
need to catch these in our double splitting pass for the vec4 backend. However,
I am a bit confused here because nir_lower_locals_to_regs injects nir_registers
and not SSA definitions so the double splitting pass can't handle the generated
NIR after it at the moment:

decl_reg vec4 64 r0[4]
(...)
vec4 64 ssa_6 = intrinsic load_ubo (ssa_0, ssa_5) () ()
r0[3] = imov ssa_6
(...)
vec4 64 ssa_12 = imov r0[0 + ssa_11]

If this is correct and expected, then I guess we will have to amend the double
splitting pass to handle nir_registers as well, right?

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