[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #52 from Iago Toral <itoral at igalia.com> ---
(In reply to Iago Toral from comment #51)
> I noticed that nir_lower_locals_to_regs can insert MOVs of 64-bit things and
> we need to catch these in our double splitting pass for the vec4 backend.
> However, I am a bit confused here because nir_lower_locals_to_regs injects
> nir_registers and not SSA definitions so the double splitting pass can't
> handle the generated NIR after it at the moment:
> 
> decl_reg vec4 64 r0[4]
> (...)
> vec4 64 ssa_6 = intrinsic load_ubo (ssa_0, ssa_5) () ()
> r0[3] = imov ssa_6
> (...)
> vec4 64 ssa_12 = imov r0[0 + ssa_11]
> 
> If this is correct and expected, then I guess we will have to amend the
> double splitting pass to handle nir_registers as well, right?

Or maybe we should split dvec3/4 loads into two dvec2 loads plus a 64-bit 
vec3/4 operation. So far I was working with the assumption that vecN operations
and dvec loads where the two cases where the vec4 backend could see writes
bigger than a dvec2. I actually implemented that for UBOs and SSBOs but seeing
this, maybe it is better to split them into dvec2 loads.

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