[Bug 92760] Add FP64 support to the i965 shader backends
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Mon Jan 11 10:02:36 PST 2016
https://bugs.freedesktop.org/show_bug.cgi?id=92760
--- Comment #30 from Jason Ekstrand <jason at jlekstrand.net> ---
Created attachment 120957
--> https://bugs.freedesktop.org/attachment.cgi?id=120957&action=edit
NIR indirect lowering pass
(In reply to Iago Toral from comment #29)
> Hey Jason/Connor,
>
> the lowering of trunc for doubles has some code that looks like this
> (pseudo-code):
>
> if (exponent < 0) {
> mask = 0x0
> } else if (exponent > 52) {
> mask = 0x7fffffffffffffff;
> } else {
> /* This is a 64-bit integer op, needs to be split into hi/lo 32-bit ops */
> mask = (1LL << frac_bits) - 1;
> }
>
> The current implementation I have works fine using bcsel. It looks something
> like this (again, pseudo-code):
>
> mask = bcsel(exponent < 0,
> 0x7fffffffffffffff,
> bcsel(exponent > 52,
> 0x0000000000000000,
> (1LL << frac_bits) -1))
>
> My problem with this is that "(1LL << frac_bits) - 1" is a 64-bit integer
> operation that we have to implement in terms of hi/lo 32-bit integer
> operations (at least until we support 64-bit integers), so it is really a
> bunch of instructions. Because I use bcsel, it means that we generate code
> for that even if exponent is not in [1..51], which is not ideal.
Right. I would encourage you not to use if's too much because branching may be
more expensive than bcsel depending on what paths different invocations take.
However, if one side of the if is overwhelmingly more likely than the other,
then control-flow is probably a good idea.
> I was thinking about rewriting this as an if/else ladder instead, however, I
> noticed that because this occurs in SSA mode I would have to deal with the
> phi nodes etc manually and I don't see any other case where we do something
> like that outside the NIR to SSA pass, so I wonder if this is actually a
> good idea at all. What do you think?
>
> If you think the if/else ladder is the way to go, is there any documentation
> or
> code references I can look at to have an idea as to how that should be
> implemented for a lowering pass in SSA mode?
I attached a pass that I've written recently (not yet sent out for review, but
it does work) that does exactly this. It replaces indirect load/store
operations with if-ladders and phi nodes (if needed). Most of it comes down to
using nir_insert_cf_node to insert it at the builder's cursor and then making
sure you set the cursor to something reasonable when you're done.
--
You are receiving this mail because:
You are the QA Contact for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freedesktop.org/archives/intel-3d-bugs/attachments/20160111/5ac82585/attachment-0001.html>
More information about the intel-3d-bugs
mailing list