[Bug 92760] Add FP64 support to the i965 shader backends
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Mon Jan 11 07:20:38 PST 2016
https://bugs.freedesktop.org/show_bug.cgi?id=92760
--- Comment #29 from Iago Toral <itoral at igalia.com> ---
Hey Jason/Connor,
the lowering of trunc for doubles has some code that looks like this
(pseudo-code):
if (exponent < 0) {
mask = 0x0
} else if (exponent > 52) {
mask = 0x7fffffffffffffff;
} else {
/* This is a 64-bit integer op, needs to be split into hi/lo 32-bit ops */
mask = (1LL << frac_bits) - 1;
}
The current implementation I have works fine using bcsel. It looks something
like this (again, pseudo-code):
mask = bcsel(exponent < 0,
0x7fffffffffffffff,
bcsel(exponent > 52,
0x0000000000000000,
(1LL << frac_bits) -1))
My problem with this is that "(1LL << frac_bits) - 1" is a 64-bit integer
operation that we have to implement in terms of hi/lo 32-bit integer operations
(at least until we support 64-bit integers), so it is really a bunch of
instructions. Because I use bcsel, it means that we generate code for that even
if exponent is not in [1..51], which is not ideal.
I was thinking about rewriting this as an if/else ladder instead, however, I
noticed that because this occurs in SSA mode I would have to deal with the phi
nodes etc manually and I don't see any other case where we do something like
that outside the NIR to SSA pass, so I wonder if this is actually a good idea
at all. What do you think?
If you think the if/else ladder is the way to go, is there any documentation or
code references I can look at to have an idea as to how that should be
implemented for a lowering pass in SSA mode?
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