[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #40 from Iago Toral <itoral at igalia.com> ---
(In reply to Kenneth Graunke from comment #39)
> There are a few bugs left with INTEL_SCALAR_GS=1 - I just filed bugs for
> them:
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=93859
> https://bugs.freedesktop.org/show_bug.cgi?id=93860
> 
> The tessellation control shader (TCS) currently operates in vec4 mode on all
> hardware.  I have a branch that begins implementing a SIMD8 backend, but I
> haven't finished it, as I don't think there's much advantage over SIMD4x2
> mode.  However, I believe everything *could* run in SIMD8 mode if we wanted.
> I could probably be talked into finishing it, if you need it.

Not really, we have been focusing on the FS backend for now for the fp64
implementation and if we could make Broadwell work  exclusively in scalar mode
that would mean that we would have it fully covered (the implementation of fp64
in the FS backend is mostly done). But the plan was to work on the vec4 backend
next anyway (we are going to need that in any case if we aim to support fp64 in
gen7 at some point) so this only means that claiming full fp64 support in
Broadwell will have to wait until we get the vec4 support in place.

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