[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #65 from Iago Toral <itoral at igalia.com> ---
> fs_reg setup_imm_df(double v) {
>    vgrf<double> tmp;
>    tmp = retype(tmp, unsigned)
> 
>    vgrf<double> v_low, v_high;
>    v_low = retype(tmp, unsigned)
>    v_high = retype(tmp, unsigned)
> 
>    mov(v_low, brw_imm_ud(low32(v)));
>    mov(v_high, brw_imm_ud(high32(v)));

Just to be clear, these two MOVs above move to both reg_offset 0 and reg_offset
1, so they write both SIMD registers allocated for both v_low and v_high.

>    mov(stride(tmp, 2), stride(v_low, 2));
>    mov(stride(horiz_offset(tmp, 1), 2), stride(v_high, 2));
> 
>    return retype(tmp, double)
> }

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